EDN

Design of a FPGA Configurable Logic Block for minimum energy and delay

Complete Layout, Design and Optimization of a FPGA Configurable Logic Block for minimum energy and delay: The CLB can function as one 8-bit adder, two 4-bit adders, a subtractor, multiplier, counter ...
EDN

Implementing 7 Series FPGAs Configurable Logic Block User Guide

Xilinx 7 series FPGAs include three FPGA families that are all designed for lowest power to enable a common design to scale across families for optimal power, performance, and cost. This guide serves ...
Electronic Design

Configurable Logic Solutions Wed FPGA Flexibility With ASIC Efficiency

An ASIC's or FPGA's ability to meet an application's demands comes down to a complex tradeoff between performance, density, time-to-market, and cost. Yet Leopard Logic combines FPGA flexibility with ...
Design-Reuse

Leopard Logic and TSMC enable configurable silicon platforms based on hyperblox FP embedded FPGA cores

CUPERTINO, CALIF AND SAN JOSE, CALIF. - November 22, 2002, -- Leopard Logic, Inc., a provider of embedded programmable logic solutions, and Taiwan Semiconductor ...
Design-Reuse

eASIC Announces Implementation of Its Configurable Logic Core in UMC's 0.15 Micron Process

SAN JOSE, Calif.--(BUSINESS WIRE)--Aug. 20, 2001-- eASIC Corporation today announced that it has completed the implementation of its eASICore, a configurable logic core, using UMC's 0.15 micron, 7 ...
Electronic Design

Fast-Turn Alternatives To FPGAs

ASIC suppliers have long noted the advantages FPGAs can offer in getting a solution to market a lot faster than a traditional full-custom design. By combining the advantages of ASIC technology and ...